1. Field of the Invention
The present invention generally relates to semiconductor memory devices and, more particularly, relates to cell structures in a static random access memory where integration density of memory cells can be increased.
2. Description of the Background Art
FIG. 39 is an equivalent circuit diagram of one memory cell in a conventional static random access memory (hereinafter referred to as SRAM). This memory cell includes six MOS transistors. A pair of driver (for driving) transistors Q.sub.1 and Q.sub.2 (n-type MOS transistors) are connected to a pair of load transistors Q.sub.5 and Q.sub.6 (p-type MOS transistors) to form a flipflop circuit. The sources 110 and 111 of the pair of load transistors Q.sub.5 and Q.sub.6 are connected to a power supply Vcc and the sources 112 and 113 of driver transistors Q.sub.1 and Q.sub.2 are connected to GND. A pair of access transistors Q.sub.3 and Q.sub.4 (n-type MOS transistors) are connected to storage nodes 114 and 115, respectively. A bit line 107 is connected to one source/drain of access transistor Q.sub.3 and a bit line 108 is connected to one source/drain of access transistor Q.sub.4. The gates of access transistors Q.sub.3 and Q.sub.4 are connected to a word line 109.
FIGS. 40 to 42 are plan views of the structure of an SRAM, showing three stages in order from the bottom on the surface of the substrate, respectively. FIG. 43 is a cross-sectional view of the structure taken along the line A--A in FIGS. 40 to 42. Referring to FIGS. 39, 40 to 43, a pair of driver transistors Q.sub.1 and Q.sub.2 and a pair of access transistors Q.sub.3 and Q.sub.4 are formed on a main surface of a p-type silicon substrate 148 of the memory cell. Driver transistor Q.sub.1 includes a pair of source/drain regions 121 and 122 and a gate electrode 125. Driver transistor Q.sub.2 includes a pair of source/drain regions 118 and 117 and a gate electrode 126. Access transistor Q.sub.3 includes a pair of source/drain regions 119 and 120 and a gate electrode 109. Access transistor Q.sub.4 includes a pair of source/drain regions 116 and 117 and a gate electrode 109. These transistors are n-type MOS transistors having source/drain regions formed on the main surface of p-type silicon substrate 148. Gate electrode 126 of driver transistor Q.sub.2 is connected to source/drain region 120 of access transistor Q.sub.3 through a contact 128. Gate electrode 126 of driver transistor Q.sub.2 is connected to source/drain region 121 of driver transistor Q.sub.1 through a contact 129. Gate electrode 125 of driver transistor Q.sub.1 is connected to source/drain region 117 of access transistor Q.sub.4 and source/drain region 117 of driver transistor Q.sub.2 through a contact 127. A gate electrode 130 of a load transistor Q.sub.5 is connected to a source/drain region 137 of a load transistor Q.sub.6 through a contact 139. A gate electrode 131 of load transistor Q.sub.6 is connected to a source/drain region 134 of load transistor Q.sub.5 through a contact 138.
A bit line 107 is connected to source/drain region 119 of access transistor Q.sub.3 through a contact 146 and a bit line 108 is connected to source/drain region 116 of access transistor Q.sub.4 through a contact 147.
As stated above, in the memory cell of the conventional SRAM, four n-type MOS transistors are arranged on the silicon substrate and p-type thin film transistors are provided as loads above them. A case where a p-type thin film transistor is used as a load of a memory cell in an SRAM has been described in IEDM 1990 Technical Digest pp. 477-480. FIG. 45 is a cross-sectional view of a typical structure of a thin film transistor used as load transistors Q.sub.5 and Q.sub.6. The thin film transistor has a channel region 142 and a pair of source/drain regions 141 and 143 formed in a semiconductor layer such as polycrystalline silicon and a gate electrode 140 provided opposite to channel region 142 with an insulating layer interposed therebetween. FIG. 46 is a diagram showing a current characteristic of the thin film transistor.
In such an SRAM, it is necessary to reduce an area occupied by each memory cell in order to increase the integration density of the memory cells. However, the conventional memory cell above had two problems to be described below.
The first problem is that it is difficult to reduce an element isolation region between transistors making up the memory cell. FIG. 44 is a diagram showing by a model a cross-section of the structure of a LOCOS film 124 (FIG. 43) for insulating and isolating transistors from each other in the memory cell shown in FIG. 43. In this LOCOS film 152 (FIG. 44), regions X called "bird's beak" are formed at its both ends, which expand to the region where elements are formed, so that an isolation width W becomes larger than its desired value. For this reason, the width of the isolation region cannot be reduced, so that reduction in the size of the memory cell cannot be achieved.
The second problem concerns a current handling capability ratio .beta. of a driver transistor to an access transistor (=the current handling capability of the driver transistor/the current handling capability of the access transistor). If the current handling capability ratio .beta. is small, data is destroyed when it is read out from a memory cell. This phenomenon will now be described below. FIGS. 47(a) and (b) show two inverter circuits obtained by dividing the equivalent circuit of the memory cell shown in FIG. 39 in connection with the reading characteristic. In this case, load transistors Q.sub.5 and Q.sub.6 are not shogun because the amount of the current flowing through these load transistors is little enough to be ignored compared with those of the access transistors and the driver transistors, so that is has no effect on the reading operation. The characteristic of reading from a memory cell is given from a change in voltage at one storage node obtained by fixing the bit line and the word line at Vcc and changing the gate voltage of the driver transistor (the voltage at the other storage node). FIG. 48(a) is a diagram showing the reading characteristic in a case where the current handling capability ratio .beta. is large (about 3). The axis of abscissa represents a voltage at storage node 115 and the axis of ordinate represents a voltage at storage node 114. The curve .alpha..sub.1 represents the voltage change characteristic at storage node 114 in a case where the voltage at storage node 115 is changed. The curve .gamma..sub.1 shows the voltage change characteristic at storage node 115 in a case where the voltage at storage node 114 is changed. The curves .alpha..sub.1 and .gamma..sub.1 intersect each other at three points P.sub.1, P.sub.2 and P.sub.3. At point P.sub.3, storage node 114 has "High" data stored, and storage node 115 has "High" data stored at point P.sub.1. Point P.sub.2 is an unstable point and the condition at this point P.sub.2 is not kept at the time of reading. In the figure, a region surrounded by a circle h is called "eye of a memory cell". As the current handling capability ratio .beta. of the transistors is larger, the circle h becomes bigger and the reading operation is stabilized.
In order to reduce the size of a memory cell, the size of an access transistor or a driver transistor is reduced. The access transistor or the driver transistor is reduced in size, for example, by shortening the gate length. If the transistor width of the access transistor is reduced to 1 .mu.m or less, a so-called narrow channel effect becomes significant, so that a threshold voltage Vth of the access transistor is increased. FIG. 48(b) shows the voltage change characteristic at the storage node in a case where the threshold voltage Vth of the access transistor is increased. In FIGS. 48(a) and (b), Vcc-.theta. or Vcc-.theta.' corresponds to the threshold voltage Vth of the access transistor. As shown in FIG. 48(b), if the threshold voltage of the access transistor is increased, the curves .alpha..sub.2 and .gamma..sub.2 intersect each other at one point P.sub.2 only and the so-called "eye of a memory cell" region disappears. As a result, the stable points of the voltage at each storage node disappear, and data stored in the memory cell is destroyed at the time of the reading operation. For these reasons, the access transistor cannot be reduced in size even though the size of the driver transistor can be reduced. If only the driver transistor is reduced in size, the current handling capability ratio .beta. of both transistors becomes small, making the reading operation unstable.